1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor memory device which performs a refresh operation.
2. Description of the Related Art
Semiconductor memory devices such as double data rate synchronous DRAM (DDR SDRAM) include memory banks for storing data. Each of memory banks includes tens of millions or more memory cells. Each of the memory cells includes a cell capacitor and a cell transistor. The semiconductor memory device stores data by charging and discharging the cell capacitor. The amount of charge stored should theoretically remain constant. However, in actuality, the charge stored in the cell capacitor changes due to voltage differences between the cell capacitor and peripheral circuits. That is, a charged capacitor may leak current or a discharged cell capacitor may gain a charge. A change in the amount of charge in the cell capacitor corresponds to a change in the data value of the memory cell, which means that the stored data may be lost. A semiconductor memory device performs a refresh operation in order to prevent this phenomenon from occurring. Refresh operations are already well known in the art and will not be described here in detail.
As process technology is developed, integration of semiconductor memory devices continues to increase. An increase in the degree of integration of semiconductor memory devices has played a pivotal role in reducing the size of memory banks. However, a reduction in the size of memory banks means that the interval between memory cells is reduced. As the interval between the memory cells is reduced, the possibility that adjacent memory cells may disturb each other increases. Accordingly, in recent years, attention has been focused on different methods for improving refresh operations.